Generally, in a semiconductor memory such as an SRAM, a density of layout pattern of a memory cell is higher than a density of layout pattern of a peripheral circuit. Accordingly, a photo resist is likely to be deformed, in a boundary between a memory cell array and the peripheral circuit, due to an effect of halation or the like. In recent years, in accordance with a microfabrication of device structure, a shape of the photo resist becomes smaller, resulting that the photo resist becomes likely to be deformed or a position thereof becomes likely to be displaced. For example, if a photo resist used for forming a gate or the like of a transistor is deformed, the transistor may not operate normally. In particular, a memory cell located on a peripheral part of the memory cell array is susceptible to the halation, and thus is likely to be a defect. In order to prevent a defect caused by this type of deformation or positional displacement of the photo resist, a method of disposing dummy memory cells around the memory cell array has been proposed (for instance, refer to Japanese laid-open Patent Publication No. 61-214559).
A dummy memory cell is disposed for preventing a deformation and a positional displacement of a gate of a transistor or a wiring pattern formed on a semiconductor substrate. Meanwhile, the dummy memory cell cannot prevent a deformation of a shape of a well region formed on a surface of the semiconductor substrate. Generally, the dummy memory cell has a same layout structure as that of a real memory cell that holds data. For this reason, if a photo resist that forms the well region is deformed, or a position of the photo resist is displaced, the dummy memory cell close to an end portion of the well region may flow an abnormal power supply current even when a shape of the gate or the like is normal (leak failure). For example, if a photo resist is deformed in a manufacturing process for forming an n-type well region on the semiconductor substrate, and an opening size of the photo resist for forming the n-type well region is increased, the n-type well region becomes large. Accordingly, if a diffusion area (a source and a drain of a transistor of the dummy memory cell) of a p-type well region adjacent to a boundary of the n-type well region is short-circuited with the n-type well region, an unexpected leak current (power supply current) is flown. This current may trigger a latch up.
A proposition of the present embodiments are to prevent, in a semiconductor memory having dummy memory cells, an abnormal power supply current from being flown into the dummy memory cells even when a well region is not formed normally.